Generating a combination exerciser for executing tests on a circuit
US8224614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2009 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Dec 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.