Data packet access control apparatus and method thereof
US8225026B2 · kind B2 · utility
0Cited by
9References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2010 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Nov 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is used as a first-level cache for small amount of data, and an external RAM of the data packet processing chip is used as a second-level cache for large amount of data. In this way, some data packets are read and written within the chip and not all data packets have to be read and written through the external RAM. A data packet reading/writing operation may be performed to the external RAM by a BANK interleave mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.