Tolerant in-system programming of field programmable gate arrays (FPGAs)
US8225153B2 · kind B2 · utility
5Cited by
13References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2006 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Apr 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fault tolerant programming of a programmable device advantageously occurs via a host controller that first queries the programmable device through a Boundary scan interface to identify the device. Thereafter, host controller selects a program file in accordance with the device identity for subsequent downloading via the Boundary scan interface to program the device. Thereafter, the host controller verifies that successful programming has occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.