Static formal verification of a circuit design using properties defined with local variables
US8225249B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2008 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | May 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static formal verification tool is used to test properties for a circuit design, where the properties are written in a verification language, such as SystemVerilog, that allows local variables. The use of local variables presents implementation challenges for static formal verification tools because it requires multiple instances of the local variables to be tracked during the verification process. To deal with local variables, the static formal verification tool translates a property containing local variables into an optimized, statically allocated data structure that does not need multiple representation of different instances of the local variables. The formal verification is then performed using the data structure. This reduces the verification complexity and makes the size of the problem representation predictable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.