Programmable analog tile placement tool
US8225260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2009 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Sep 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.