Method of fabricating a transistor with semiconductor gate combined locally with a metal
US8227342B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 10, 2008 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Oct 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a field effect transistor comprising a gate formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone and lateral zones in the length of the gate, the method comprising forming a gate comprising a portion of insulating layer, a portion of semiconducting layer formed over the insulating layer, and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the center of the gate remains; and reacting the semiconducting gate with a metal deposited over the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.