Semiconductor memory device including resistance-change memory
US8227784B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Nov 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes first lines and second lines and a memory cell array. The first lines and second lines are formed to intersect each other. The memory cell array includes memory cells arranged at intersections of the first lines and the second lines and each formed by connecting a rectification element and a variable-resistance element in series. The rectification element includes a first semiconductor region having an n-type and a second semiconductor region having a p-type. At least a portion of the first semiconductor region is made of a silicon-carbide mixture (Si1-xCx (0<x<1)), and the second semiconductor region is made of silicon (Si).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.