Integrated circuit resistive devices including multiple interconnected resistance layers
US8227897B2 · kind B2 · utility
18Cited by
1References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 3, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Feb 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.