Phase-locked loop architecture and clock distribution system

US8228102B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Tien Duc Pham · San Jose, US
• Sergey Shumarayev · Los Altos Hills, US
• Richard G. Cliff · Milpitas, US
• Tim Tri Hoang · San Jose, US
• Weiqi Ding · Fremont, US
• Sriram Narayan · Pleasanton, US
• Thungoc M. Tran · San Jose, US
• Kumara Tharmalingam · Los Gatos, US

Key dates

• Filing date: Mar 3, 2010
• Grant date: Jul 24, 2012
• Expiry date: Sep 25, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/1974
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.