Clock signal correction
US8228105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Jan 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.