On-chip self calibrating delay monitoring circuitry
US8228106B2 · kind B2 · utility
11Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Jan 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to on-chip self calibrating delay monitoring circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.