Semiconductor memory device and a method of operating thereof
US8228708B2 · kind B2 · utility
3Cited by
1References
6Claims
0Family size
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Key dates
| Filing date | Aug 31, 2011 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Aug 31, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the operating method of the semiconductor memory device, (1) voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2>Vs, and V2>Vd, are applied to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode to write a first resistance value, respectively, (2) the voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2<Vs, and V2<Vd, are applied to write a second resistance value, and (3) the voltages V1, V2, Vs, and Vd, which satisfy V1<Vs, V1<Vd, V2<Vs, and V2<Vd, are applied to write a third resistance value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.