Programming method for multi-level cell flash for minimizing inter-cell interference
US8228728B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods and computer program products for minimizing floating gate coupling interference and threshold voltage drift associated with flash memory cells are described. In some implementations, the memory cells can be programmed in a predetermined sequence that allows pages with the most-significant bit (MSB) and central significant bit (CSB) to be programmed first prior to programming pages with the least-significant bit (LSB). This sequence allows neighboring cells (e.g., cells neighboring a target cell) to be programmed first so as to reduce the floating gate coupling interference and threshold voltage drift on the target cell that is to be programmed in the subsequent stage. To accommodate the programming sequence (e.g., at the device level), additional buffer memories can be added.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.