Hardware accelerated transactional memory system with open nested transactions
US8229907B2 · kind B2 · utility
129Cited by
34References
10Claims
0Family size
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Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | May 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/2379
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware assisted transactional memory system with open nested transactions. Embodiments include a system whereby hardware acceleration of transactions can be accomplished by implementing open nested transaction in hardware which respect software locks such that a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional memory systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.