Data throughput optimization of a storage device having sequential data access
US8230175B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2005 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | May 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method optimizing data throughput to a processor from a storage device having sequential data access capabilities where the processor enables its data cache for memory operations involving the storage device. The system includes a processor coupled to the data storage device, e.g., a NAND flash memory. The processor establishes an address window used as a cache (CW) for reading data from the flash memory and also establishes a non-cacheable address window (NCW) for commands, address delivery and writes to the flash memory. The CW is sized to be larger than the processor data cache to ensure that reads from the flash memory always encounter a cache-miss so that read data is obtained directly from the flash memory. By reading through the CW from the flash memory, the processor takes advantage of bursting, pipelining and data prefetch efficiencies which significantly increase data throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.