Reconfigurable cache
US8230176B2 · kind B2 · utility
9Cited by
11References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Sep 2, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a large routing structure. The cache controller includes an additional address decoder for the small cache with a smaller routing structure. The additional address decoder for the small cache reduces decode, array access, and data return latencies. When only a small cache is actively in use, the rest of the cache can be turned into low-power mode to save power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.