Interleaving scheme for an LDPC coded QPSK/8PSK system
US8230299B2 · kind B2 · utility
23Cited by
9References
6Claims
0Family size
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Key dates
| Filing date | Mar 1, 2010 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Apr 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/43
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An approach is provided for interleaving low density parity check (LDPC) encoded bits in QPSK/8PSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.