Low-power predecoding based viterbi decoding
US8230313B2 · kind B2 · utility
1Cited by
13References
19Claims
0Family size
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Key dates
| Filing date | Aug 10, 2009 |
| Grant date | Jul 24, 2012 |
| Priority date | — |
| Expiry date | Nov 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/47
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.