Method for manufacturing and testing an integrated electronic circuit
US8232113B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 20, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | May 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.