Clock circuit and method for pulsed latch circuits
US8232824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2010 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Oct 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.