Techniques for multiplexing delayed signals
US8232826B1 · kind B1 · utility
1Cited by
2References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2010 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Oct 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit with N primary outputs and a delay chain with M selection multiplexers. M can be less than N, and M is based on the number of primary outputs that simultaneously require a delayed signal from the delay chain. The N primary outputs may include core outputs and/or registers. Each of the M selection multiplexers feed directly or indirectly a subset of the N primary outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.