Integrated circuit including a large number of identical elementary circuits powered in parallel
US8232836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Mar 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00369
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to an integrated circuit comprising a succession of N identical elementary circuits (CE1, CE2, . . . CEN), juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V0 supplied by two conductors. An upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and an upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. The integrated circuit is applicable to analog-digital converters or digital-analog converters with high resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.