ESD protection circuit for low voltages
US8233252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2006 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jan 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit is provided having a first field-effect transistor, which has a first drain terminal, a first source terminal and a first control terminal, and having an input network which, in the event that a first voltage present between the first drain terminal and the first source terminal crosses a threshold value, alters a second voltage that appears between the first control terminal and the first source terminal. The input network contains a second field-effect transistor, complementary to the first field-effect transistor, having a second drain terminal, a second source terminal and a second control terminal, wherein the first drain terminal is connected to the second source terminal and, through a first resistance, to the second control terminal, and the second drain terminal is connected to the first control terminal and, through a second resistance, to the first source terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.