Multi-die memory device
US8233303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2007 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | May 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.