Interfaces, circuits, and methods for communicating with a double data rate memory device
US8234422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.