Interrupt masking for multi-core processors
US8234431B2 · kind B2 · utility
59Cited by
42References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 13, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Nov 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.