Systems and methods for maintaining lock step operation
US8234521B2 · kind B2 · utility
13Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jan 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.