Iterative decoder using input data pipelining and time-interleaved processing
US8234536B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2008 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | May 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one implementation, a decoding architecture is provided that includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder coupled to the input buffer. The decoder is configured to receive a first codeword and a second codeword from the input buffer, and simultaneously process the first codeword and the second codeword such that each of the first codeword and the second codeword is processed only for a minimum amount of time for the first codeword or the second codeword to become decoded. The input buffer is further configured to load a third codeword into the decoder responsive to the first codeword or the second codeword being decoded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.