Scalable packet processing systems and methods
US8234653B1 · kind B1 · utility
2Cited by
12References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2008 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | Jun 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/60
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data across the processors. Appropriate ones of the processors are configured to process the data. The reorder logic is configured to receive the data processed by the processors, reorder the data, and output the reordered data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.