Method of fabricating a semiconductor device having gate finger elements extended over a plurality of isolation regions formed in the source and drain regions
US8236640B2 · kind B2 · utility
10Cited by
5References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Oct 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.