Source and drain feature profile for improving device performance and method of manufacturing same
US8236659B2 · kind B2 · utility
33Cited by
8References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jun 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.