Methods of fabricating vertical semiconductor device utilizing phase changes in semiconductor materials
US8236673B2 · kind B2 · utility
8Cited by
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20Claims
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Key dates
| Filing date | Feb 10, 2011 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Feb 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.