Semiconductor device and method of manufacturing the same
US8237222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2010 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jan 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/314
Abstract
In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.