Efficient switch cascode architecture for switching devices
US8237422B2 · kind B2 · utility
6Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Oct 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/088
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Efficient switch cascode architecture for switching devices, such as switching regulators. The cascode architecture includes a switching stage responsive to an external driver signal for switching transitions, and a bias generator operative to bias the cascode transistor of the switching stage to protect the switching stage from damage during the switching transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.