Patent · US Active

Method for wafer-level testing of integrated circuits

US8237462B2 · kind B2 · utility

8Cited by

3References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Tsung-Yang Hung · Dashulong, TW
Aaron Wang · Baoshan, TW

Key dates

Filing date	Aug 11, 2009
Grant date	Aug 7, 2012
Priority date	—
Expiry date	Sep 21, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2831
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.