Programmable clock generator used in dynamic-voltage-and-frequency-scaling (DVFS) operated in sub- and near- threshold region
US8237477B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2011 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | May 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable clock generator, which is used in dynamic-voltage-and-frequency-scaling (DVFS) operated in Sub- and Near-Threshold region. The programmable clock generator includes first pulse generating unit and a pulse multiplier. A first counter is configured to generate a first counting signal, so as to control the phase detector comparing the phase difference between a first pulse signal and a second pulse signal. A first control signal is transmitted by a control unit in accordance with a phase difference signal, and the phase of the second pulse signal is adjusted by a lock-in delay unit, so that a predetermined phase is generated between the first pulse signal and the second pulse signal. The PVT variation may be compensated by the programmable clock generator during the sub threshold region. Therefore, the period of reference clock is in the locking range of lock-in delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.