Serial interface device and image forming apparatus
US8237980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2007 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | May 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/061
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.