Recovering from failures without impact on data traffic in a shared bus architecture
US8238255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2007 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jan 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0712
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods of detecting and recovering from communication failures within an operating network switching device that is switching packets in a communication network, and associated structures. The communication failures addressed involve communications between the packet processors and a host CPU over a shared communications bus, e.g., PCI bus. The affected packet processor(s)—which may be all or a subset of the packet processors of the network switch—may be recovered without affecting hardware packet forwarding through the affected packet processors. This maximizes the up time of the network switching device. Other packet processor(s), if any, of the network switching device, which are not affected by the communication failure, may continue their normal packet forwarding, i.e., hardware forwarding that does not involve communications with the host CPU as well as forwarding or other operations that do involve communications with the host CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.