Managing tap positions in a digital delay line
US8238409B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Feb 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7115
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
This method of reading a plurality of chip sample values at tap positions (66, 68) in a digital delay line (64) having a starting point and an end point for delaying symbols of a signal (82) received in a receiver comprises:—reading the plurality of chip sample values in the digital delay line (64) at the tap positions (66, 68) according to a chip rate clock (70) having a chip rate clock cycle and a chip rate clock frequency,—oversampling the received signal (82) according to a sample rate clock (84) having a sample rate clock cycle and a sample rate clock frequency to produce a plurality of chip sample values supplied in the digital delay line (64), the sample rate clock frequency being higher than the chip rate clock frequency,—shifting the tap positions (66, 68) towards either the starting point or the end point of the digital delay line (64), and—adjusting the chip rate clock cycle when shifting the tap positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.