Computing module for efficient FFT and FIR hardware accelerator
US8239442B2 · kind B2 · utility
5Cited by
5References
10Claims
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Key dates
| Filing date | Aug 8, 2008 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jun 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.