System on chip (SoC) device verification system using memory interface
US8239708B2 · kind B2 · utility
1Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | May 29, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jan 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.