Nonvolatile memory devices that utilize error correction estimates to increase reliability of error detection and correction operations
US8239747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2008 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jun 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.