Timing analyzing system for clock delay
US8239795B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 2009 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing analyzing system includes an RC extracting section configured to generate an SPEF (Standard Parasitic Exchange Format) file which contains resistance and capacitance components of wirings; a delay calculating section configured to generate an SDF (Standard Delay Format) file based on the SPEF file; and a clock mesh calculating section configured to generate a corrected circuit model by simplifying a netlist on a clock path to pass through a clock mesh structure from an input stage. A timing analysis section is configured to perform timing analysis of a semiconductor integrated circuit of an analysis target based on the corrected circuit model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.