Layout method and layout apparatus for semiconductor integrated circuit
US8239803B2 · kind B2 · utility
109Cited by
6References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 27, 2011 |
| Grant date | Aug 7, 2012 |
| Priority date | — |
| Expiry date | Jul 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout method of a semiconductor integrated circuit by using cell library data includes specifying a gate in a predetermined cell as a reference gate, and automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from the reference gate meets a preset gate data density condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.