Method and structure for copper gap fill plating of interconnect structures for semiconductor integrated circuits

US8242017B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Yang Xiang · Taiyuan, CN
• Qing Jiang · Plano, US

Key dates

• Filing date: Mar 7, 2008
• Grant date: Aug 14, 2012
• Expiry date: May 25, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76873
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming an integrated circuit device including an interconnect structure, e.g., copper dual damascene. The method includes providing a substrate and forming an interlayer dielectric layer overlying the substrate. The method also includes patterning the interlayer dielectric layer to form a contact structure and forming a barrier metal layer overlying the contact structure. The method includes forming a seed layer comprising copper bearing species overlying the barrier metal layer and applying an oxygen bearing species to treat the seed layer to cause an oxide layer of predetermined thickness to form on the seed layer. The method protects the seed layer from contamination using the oxide layer while the substrate is transferred from the step of applying the seed layer and contacts a copper bearing material in liquid form overlying the oxide layer to dissolve the oxide layer while forming a thickness of copper bearing material using a plating process to begin filling the contact structure.