Semiconductor body, circuit arrangement having the semiconductor body and method
US8242801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2006 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jun 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input circuit arrangement comprises an input, a comparator, and an evaluation circuit. The input is designed for coupling to a first terminal of an impedance and for feeding an input signal. The comparator is connected to the input of the input circuit arrangement and is designed for delivering an activation signal to an output as a function of a comparison of the input signal with an adjustable threshold. Furthermore, the evaluation circuit is connected to the input of the input circuit arrangement and for its activation to the output of the comparator and is designed for evaluating the value of the impedance that can be connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.