Methods and systems for managing a write operation
US8242806B1 · kind B1 · utility
0Cited by
7References
27Claims
0Family size
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Key dates
| Filing date | Jul 1, 2010 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jul 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for managing a write operation are described. The systems include a logic element (LE) including an N-input look-up table (LUT) having a configurable random access memory (CRAM) including 2N memory cells. The systems further include a write address decoder coupled to the LE and a write address hard logic register that stores an address of one of the memory cells. N is an integer. The hard logic register removes a dependency of a timing relationship between a write address launch and a write to the CRAM on a design of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.