Fast settling, bit slicing comparator circuit
US8242810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Oct 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/082
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved fast settling bit slicing comparator circuit includes a comparator having a non-inverting and inverting input; the non-inverting input receiving an input signal; a filter circuit for receiving the input signal and being connected with the inverting input of the comparator; a positive feedback circuit interconnected between the output of the comparator and the non-inverting input of the comparator for introducing a predetermined hysteresis offset; the filter circuit including a filter resistance and filter capacitance having a reduced time constant sufficient to compensate for at least a portion of the hysteresis offset. Additionally, the positive feedback circuit may be interconnected with the inverting input of the comparator through the filter circuit for gradually reducing the effect of the hysteresis offset by reducing the differential voltage between the inverting and non-inverting inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.