High speed packet FIFO input buffers for switch fabric with speedup and retransmit
US8243737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2010 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jan 31, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/111
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.