Scheduler using a plurality of slow timers
US8243760B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Jul 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
There is disclosed a scheduler for a traffic generator and a method of scheduling traffic. A working memory may stores N respective timer values for N count-down timers, where N is an integer greater than one. An arithmetic and logic unit (ALU) may update each timer value in rotation every N cycles of a clock. A temporal interpolator may delay output data from the ALU by a selectable delay period of 1 to N cycles of the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.